Computer Systems and Platforms Lab

Faculty: Bernhard Egger
Office: 
301 Building, Room 412
Phone: 
(02) 880-1819
Fax: 
(02) 886-7589

In the Computer Systems and Platforms Laboratory at Seoul National University, we focus on future computer systems and platforms for (mostly embedded) computing devices. As more and more cores are integrated into one single chip, the architectural changes not only require new operating system structures but also compilers and programming languages that enable developers to exploit the computing power of the chip while at the same time providing an efficient development environment.

We envision a future where portable computing systems are composed of heterogeneous many-core processors that process data from a variety of sensors. Such systems will run standard tasks alongside safety-critical and secure applications such as heart-rate monitoring or internet banking. To use such systems in an efficient and secure manner, a holistic approach that coordinates research on all levels from the architecture, to the compiler, the operating system up to the programming environment and the programming language is necessary.

We currently conduct research in the following areas:
• compilers and runtime-environments for next-generation many-core coarse-grained reconfigurable architectures
• secure and energy-aware operating systems for future mobile systems with heterogeneous many-cores
• virtualization techniques on many-core systems

Coarse-grained reconfigurable architectures (CGRA)

CGRAs are composed of several computing units and register files with a configurable interconnection network. CGRAs combine the flexibility of software with the performance of parallel hardware.

  • Chip Verification

This is an important area of CGRA research. We are researching compiler-assisted generation of random test codes that enables hardware manufacturers to quickly and efficiently verify the functional correctness of their CGRA hardware design.

  • NUMA many-core CGRA

In this project, we are researching various task distribution algorithms for a many core CGRA system with non-uniform memory access latency. A good task distribution is key to exploiting the full potential and achieving the expected performance. Based on a model of the architecture, we construct task distribution algorithms that are then verified on an FPGA implementation of a 16-core CGRA.

Operating systems for heterogeneous many-core processors

Managing a large number of heterogeneous independent cores with the goal to provide maximal performance at a minimal energy consumption poses lots of interesting new challenges for operating system architects.

Energy-aware Runtime Systems Many-core processors offer various mechanisms to conserve energy. In this project, we develop a hierarchical power management technique that combines power management with operating system/process migration to achieve maximal power savings. We evaluate our method on Intel’s Single Chip Cloud computer many-core prototype. Virtualization is another key technology for many-core systems. We have published methods to reduce the time and size of snapshots of virtual machines. We are currently working on techniques to significantly reduce the time it takes to migrate a virtual machine from one physical host to another

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