[Seminar] GraphGen : Design Compiler for Graph Computations

Eriko Nurvitadhi
Intel Science and Technology Center
2013년 2월 6일 수요일 PM 2:00 - 2013년 2월 6일 수요일 PM 3:00
Room 551, Building 301


Many important emerging applications in machine learning and data mining (MLDM) can be cast as graph computations. For example, belief propagation (BP) algorithms commonly used in computer vision are often formulated as message passing over edges of vertices in a graph that represent the pixels of images. Efficient implementations of graph computations promise disruptive capabilities for the increasingly ubiquitous embedded and mobile platforms (e.g., smart phones, smart glasses, etc). The tight power and cost budgets of these embedded systems, coupled with their stringent real‐time performance requirements, are best satisfied through special‐purpose hardware acceleration. However, developing special‐purpose hardware design for the myriad of graph applications would be costly in time and effort. This talk will present GraphGen, a design compiler that automatically maps a given high‐level specification of graph computation onto efficient accelerator‐based platforms. The specification adopts the vertex‐centric GraphLab abstraction, which is flexible to capture arbitrary graph applications, and is already widely used in MLDM communities. Through automation, GraphGen reduces development time and effort. Further, it makes hardware acceleration of general graph computation a viable option for application‐level and algorithmic‐level developers who are not hardware design experts. To illustrate the benefits of GraphGen, the talk will report on a design case study using GraphGen to implement the aforementioned BP algorithm onto two different embedded FPGA‐acceleration platforms (Intel Stellarton and Xilinx ML605).

연사 소개

Eriko Nurvitadhi is a researcher in the Intel Science and Technology Center for Embedded Computing (www.istc‐ec.org). His research interests are at the intersection of computer architecture, design automation, and reconfigurable logic (FPGAs). Eriko has a PhD in Electrical and Computer Engineering from Carnegie Mellon University and an MBA from Oregon State University.

  • Contact : Prof. Jaejin Lee (02-880-1863)