Designing Multicores for Programmability: The Bulk Multicore Architecture
One of the biggest challenges facing computer architecture today is the design of parallel architectures that efficiently support programmable environments. The Bulk Multicore is designed for programmability while delivering high performance. It is based on the idea of eliminating the commit of individual instructions and, instead, working on atomic chunks of instructions. This approach enables new code transformations and a novel infrastructure for parallel application development, debugging, and tuning.
Josep Torrellas is Professor of Computer Science and (by courtesy)Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC). He is a Fellow of IEEE and ACM. At UIUC, he is the Director of the Center for Programmable Extreme-Scale Computing, and of the Illinois-Intel Parallelism Center. He received a Ph.D. from Stanford University. He has made contributions to parallel computer architecture in the areas of shared-memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He is currently involved in designing energy-efficient extreme-scale computers. He has lead the I-ACOMA multiprocessor project and been involved in the DARPA-funded IBM-PERCS multiprocessor, and the Stanford DASH and Illinois Cedar machines.