[Seminar] Guidelines to Design Parity Protect Write-back L1 Data Cache

이경우(Kyoungwoo Lee)
associate professor
Yonsei University
Tuesday, August 29th 2017, 2:00pm - Tuesday, August 29th 2017, 3:00pm
32-1 Haedong hall

■ 호스트: 이창건 교수(x1862, 880-1862)


Several decades of technology scaling has brought the challenge of soft errors to modern computing systems, and caches are most susceptible to soft errors. While it is straightforward to protect L2 and other lower level caches using error correcting coding (ECC), protecting the L1 data caches poses a challenge. Parity-based protection of L1 data cache is a more power-efficient alternative, however, some questions still linger -- How effective is parity protection for caches? How can we design a parity-based L1 data cache so as to maximize the protection achieved? To answer these questions, we need to perform a quantitative evaluation of the protection afforded by various parity-protected cache design alternatives, and formulate guidelines for the design of power-efficient and reliable L1 data caches. Towards this goal, we develop an algorithm to accurately model the vulnerability of data in caches, in the presence of various configurations of parity protection, and validate it aga inst extensive fault injection campaigns. We find that, (i) checking parity at reads only (and not at writes) provides 11% more protection with 30% lesser power overheads as compared to that at both reads and writes; and (ii) when implementing parity at the word-level granularity for 53% improved protection as compared to block-level parity implementation, the dirty-bits in the cache should also be implemented at the same granularity, otherwise, there is no improvement in protection. We find several popular commercial processors -- even the ones specifically designed for reliability -- not following these design guidelines, and resulting in sub-optimal designs

Speaker Bio

Kyoungwoo Lee is an associate professor in the department of computer science and engineering at Yonsei University, Seoul, South Korea. He received B.S. and M.S. degrees in computer science from Yonsei University in 1995 and 1997, respectively, and Ph.D. degree in information and computer science at the University of California at Irvine in 2008. Prior to joining Yonsei, he has experienced industries as software engineers at LG electronics, Inc. in Seoul from 1997 to 2003 and Digital Spectrum Solutions in Irvine, CA from 2009 to 2011. His research is in the area of embedded systems, with a specific focus on cross-layer design and optimization for error-aware and energy-efficient embedded systems. He has published several papers in DAC, DATE, ICCAD, ESWEEK, and ACM Multimedia.