[Seminar] SiLago: The Next Generation Synchorous VLSI Design Platform

Ahmed Hemani
Royal Institute of Technology, Sweden
Tuesday, October 17th 2017, 11:00am - Tuesday, October 17th 2017, 12:00pm

■호스트: Bernhard Egger 교수 (x1819, 880-1819)


The VLSI community faces two challenges that we propose to address with the SiLago Method. The first problem is the unsustainably large engineering cost of VLSI design that is suffocating innovation and introduction of new product categories that requires orders of magnitude greater computational and silicon efficiencies that can only be achieved by custom hardware design. This recipe goes against the current state-of-the-practice, the software centric accelerator rich platform based design style that has not only failed to reduce the engineering cost but also delivers sub-optimal designs and does not scale with technology trends. As a solution, we propose raising the abstraction of physical design platform from the present day boolean level standard cells to micro-architectural level SiLago (Silicon Large Grain Objects) blocks as the atomic physical design building blocks and introduce a grid based synchorous VLSI Design scheme discipline to compose arbitrary designs by abutting SiLago blocks to eliminate the logic and physical syntheses for the end user. Synchorous is derived from the Greek word for space – choros. Synchorous objects discretize space uniformly with the grid, the way synchronous objects discretize time with clock ticks. We call this the SiLago method and show that it provides 2-3 orders more efficient synthesis from application level compared to the standard cell based commercial design flows with a modest loss in design quality.

Speaker Bio

Ahmed Hemani is Professor in Electronic Systems Design at School of ICT, KTH, Kista, Sweden. His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis – his doctoral thesis was the basis for the first high-level synthesis product introduced by Cadence called visual architect. He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods. He has extensively worked in industry including National Semiconductors, ABB, Ericsson, Philips Semiconductors, Newlogic.