[Seminar] Rethinking Processor Architecture and Design Methodologies for Timing-Safe Information Flow Security

G. Edward Suh
School of Electrical and Computer Engineering at Cornell University
Monday, July 15th 2019, 10:30am - Monday, July 15th 2019, 11:30am
301동 201호

호스트: 안정호, 이재욱 교수


As shown by Meltdown and Spectre, modern processor architectures are vulnerable to side/covert-channel attacks that exploit hardware-level behaviors not visible in the traditional instruction set architecture(ISA). In particular, timing channels represent one of the most serious threats because they can be exploited in software without physical proximity to a victim system.

Speaker Bio

G. Edward Suh is a Professor in the School of Electrical and Computer Engineering at Cornell University. He received a Ph.D. degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT) in 2005. Before joining Cornell, he led the commercial development of the Physical Unclonable Function (PUF) technology at Veryao Inc., which is now used in commercial products such as Xilinx UltraScale+ MPSoC for storing secret keys. He also did early research work on dynamic cache partitioning and secure processor technologies, which are widely available in today's processors. His research interests span computer systems in general with a focus on developing architectural techniques to improve security and efficiency.

참고사항: 7월 17일부터 같은 장소에서 Security Architecture와 관련하여 Edward G. Suh 교수님이 다음의 Lecture Series를 진행할 예정입니다.
7/17 (Wed) 10:00am - Basic security concepts
7/19 (Fri) 10:00am - Cryptographic primitives
7/22 (Mon) 10:00am - Secure processors and off-chip memory protection
7/24 (Wed) 10:00am - Microarchitectural timing channels
7/26 (Fri) 10:00am - Physical attacks and hardware security verification