[DLS] Speculative aspects of high-speed processor design

Kei Hiraki
University of Tokyo
서울대학교 컴퓨터공학부
Monday, October 22nd 2012, 2:00pm
301동 203호


Recent speed-up of a high-performance processor is mainly realized by the introduction of speculative mechanisms to the processor design. Branch prediction, Prefetching, cache replacement policy, memory access scheduling and hardware transactional memory are examples of speculative mechanisms. In this talk, we show our recent progress in speculative mechanisms including pattern mactch based prefetching, memory access scheduling mechanisms that are the state of the art methods so far. In addition to them, we show our work on Network on Chip configuration.

Speaker Bio

Kei Hiraki is a Professor in the Department of Computer Science, Graduate School of Information and Technology at the University of Tokyo. He received a BA, MS, and Ph.D. in physics from the University of Tokyo. He then worked in the Electrotechnical Laboratory at MITI in Japan from 1982 until 1988. At this time he came to the USA to work at IBM T.J. Watson Research Center. In 1991, he returned to Japan to be a professor at the University of Tokyo. Prof. Hiraki performed wide range of research Topics including Dataflow architecture, Distributed Shared Memory, Highly-parallel architecture, and very high-speed internet communication. He currently holds all the classes of Internet2 Land Speed Records for high-speed, long-distance TCP communications.