The coming shift toward tiered memories with capacity moving away from direct-attached DRAM brings new opportunities and challenges. The opportunities for reduced system cost and tighter integration of the memory controller and DRAM are substantial, including reduced cost and processing in/near memory. However, managing data placement to mitigate higher latency and provide locality for processing while still meeting the high reliability and security demands of large-scale deployment is very challenging. Time permitting, I will discuss four recent research projects toward addressing these challenges. The first is an OS/runtime approach to quickly and cheaply identify memory access patterns and migrate data. The second relates to proactively placing memory to enable processing in/near memory for large machine-learning models (recommender models used as an example). The third provides the foundations for new directions in DRAM reliability, in particular relating to future memory syst ems and PIMs, by developing a data-driven component-level DRAM reliability model. The fourth touches upon a fundamental new approach for truly scalable memory integrity protection, which is needed for providing memories that are secure even against all direct physical attacks.

Mattan Erez is a Professor at the Chandra Family Department of Electrical and Computer Engineering at the University of Texas at Austin. His research focuses on improving the performance, efficiency, and scalability of computing systems through advances in memory systems, hardware architecture, software systems, and programming models. His current focus areas are architectures for machine learning, large-scale and high-performance computing, and memory systems. Mattan received a BSc in Electrical Engineering and a BA in Physics from the Technion, Israel Institute of Technology and his MS and Ph.D. in Electrical Engineering from Stanford University. He was awarded a Presidential Early Career Award for Scientists and Engineers from President Obama.