[Seminar] Memory Organizations for 3D Die Stacking

Gabriel H. Loh
Fellow Design Engineer
AMD Research
2014년 4월 17일 목요일 PM 4:00
Room 554, Building 301

Contact : Prof. Jaejin Lee (02-880-1863)


This talk provides a brief overview of die-stacking technologies, covering some of the different options out there for stacking. I will then focus on architectural approaches for 3D-stacked memories, as this is one of the first major application areas of die stacking. For markets that require significant memory capacity and upgradable memory, die-stacked DRAM alone will not be sufficient, which creates technical challenges for the architecture and overall system organization. This talk will focus on techniques to integrate the stacked memory in a software-transparent fashion, but we will also discuss challenges and open research directions for exposing the heterogeneity of this kind of memory system to the software stack.

연사 소개

Gabriel H. Loh is a Fellow Design Engineer in AMD Research, the research and advanced development lab for Advanced Micro Devices, Inc. Gabe received his Ph.D. and M.S. in computer science from Yale University in 2002 and 1999, respectively, and his B.Eng. in electrical engineering from the Cooper Union in 1998. Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. He is a senior member of IEEE and the ACM, (co-)inventor on over fifty US patent applications, and a recipient of the US National Science Foundation Young Faculty CAREER Award. His interests include computer architecture, processor microarchitecture, memory systems, emerging technologies, 3D die stacking, Korean food, sushi, BBQ, ice hockey, and snowboarding.