[Seminar] Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems
University of Illinois, Urbana-Champaign (UIUC)
The performance of computer systems is often limited by the bandwidth of their memory channels, but further increasing the bandwidth is challenging under the stringent pin and power constraints of packages. To further increase performance under these constraints, various near-DRAM acceleration (NDA) architectures, which tightly integrate accelerators with DRAM devices using 3D/2.5D-stacking technology, have been proposed. However, they have not prevailed yet because they often rely on expensive HBM/HMC-like DRAM devices which also suffer from limited capacity, whereas the scalability of memory capacity is critical for some computing segments such as servers. In this paper, we first demonstrate that data buffers in a load-reduced DIMM (LRDIMM), which is originally developed to support large memory systems for servers, are supreme places to integrate near-DRAM accelerators. Second, we propose Chameleon, an NDA architecture that can be realized without relying on 3D/2.5D-stacking tec hnology and seamlessly integrated with large memory systems for servers. Third, we explore three microarchitectures that abate constraints imposed by taking LRDIMM architecture for NDA. Our experiment demonstrates that a Chameleon-based system can offer 2.13 χ higher geo-mean performance while consuming 34% lower geo-mean data transfer energy than a system that integrates the same accelerator logic within the processor.
I am an associate professor at the University of Illinois, Urbana-Champaign and an IEEE Fellow. Prior to joining the University of Illinois in the fall of 2015, I was an associate professor at the University of Wisconsin, Madison where I was early-tenured in 2013. My interdisciplinary research incorporates device, circuit, architecture, and software for power-efficient computing. Prior to joining the University of Wisconsin, Madison, I was a senior research scientist at Intel from 2004 to 2008, where I conducted research in power-efficient digital circuit and process architecture. I have published more than 150 refereed articles to highly-selective conferences and journals in the field of digital circuit, processor architecture, and computer-aided design. The top three most frequently cited papers have more than 3000 citations and the total number of citations of all his papers exceeds 6400. I was a recipient of the IEEE Design Automation Conference (DAC) Student Design Contest Aw ard in 2001, Intel Fellowship in 2002, the IEEE International Symposium on Microarchitecture (MICRO) Best Paper Award in 2003, NSF CAREER Award in 2010, IBM Faculty Award in 2011 and 2012, the University of Wisconsin Villas Associates Award in 2015, and IEEE International Symposium on High-Performance Computer Architecture Best Paper Nomination in 2017. I am a member of IEEE International Symposium on High-Performance Computer Architecture (HPCA) Hall of Fame (I am the first Korean researcher in the list and a top-3 researcher in terms of the number of published paper in this conference) and IEEE International Symposium on Microarchitecture (MICRO) Hall of Fame. I earned a PhD degree in Computer Science and Engineering from the University of Michigan, Ann Arbor and Master and Bachelor degrees in Electrical Engineering from the Korea Advanced Institute of Science and Technology.