[Seminar] Die-Stacking: Evolution, Present, and Futures
호스트: 이재욱 교수 (x1834,880-1834)
Die-stacking technology has been considered for decades, but has only recently gained significant traction in high-volume commercial products. In this talk, I will start with an overview of today's current semiconductor technology environment with a focus on the trends and pressures that have opened the doors for die stacking. I will then describe die-stacking technology itself including wafer processing and through-silicon vias (TSVs). The remainder of the talk then shifts toward architecture applications of the technology. We paint a spectrum of possible architecture approaches based on TSV density, walk through some examples of die stacking in current systems, and then cover future directions, challenges, and key research opportunities related to die stacking for computer architectures.
Gabriel H. Loh is a Fellow Design Engineer in AMD Research, the research and advanced development lab for Advanced Micro Devices, Inc. Gabe received his Ph.D. and M.S. in computer science from Yale University in 2002 and 1999, respectively, and his B.Eng. in electrical engineering from the Cooper Union in 1998. Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. He is a Fellow of the ACM and IEEE, recipient of ACM SIGARCH's Maurice Wilkes Award, Hall of Fame member for the MICRO, ISCA, and HPCA conferences, (co-)inventor on over one hundred US patent applications and sixty granted patents, and a recipient of the US National Science Foundation Young Faculty CAREER Award. His research interests include computer architecture, processor microarchitecture, emerging technologies and 3D die stacking.