[Seminar] Design Challenges of Storage Systems to expose Microsecond-scale Latency

2019년 9월 27일 금요일 PM 3:00 - 2019년 9월 27일 금요일 PM 4:00
삼성전자서울대연구소 1층 대강당

호스트: 안정호 (융대원), 이재욱 교수


Data is exploding and generated more in just the last year than in the entire previous history of the industry. As non-volatile memory gets closer to processors in modern computing systems, the logical and physical boundaries between them become blurred. While the throughput performance was by far the most important metric of block storage, the latency characteristics exposed by the underlying storage are considered as a more vital parameter in the systems. In this talk, we will mainly discuss several challenges and innovative concepts to expose the microsecond-scale latency of state-of-the art solid state drive architectures. Specifically, this talk advocates radically different system-level and architecture-level approaches that expose true latency of NVM to users. The system-level approaches will discuss kernel and interface optimizations whereas the architecture-level approaches introduce our ongoing studies that implement a real phase-change memory (PRAM) integrated backend and design frontend hardware automation.

연사 소개

Dr. Myoungsoo Jung is Associate Professor at KAIST. Dr. Jung earned his Ph.D. in Computer Science at Pennsylvania State University and his M.S. in Computer Science from Georgia Institute of Technology, and an M.S. in Embedded System from Korea University in Seoul. Before joining KAIST, he was involved in Yonsei University and University of Texas at Dallas as an assistant professor. In addition, Dr. Jung has many years of industry experience, several industrial U.S. patents related to multi-channel SSDs, and approximately a hundred technical papers regarding SSD flash firmware and kernel-level file systems (mainly published OSDI, ISCA, MICRO, ASPLOS and HPCA). His research has been nominated as best paper from the Institute of Electrical and Electronics Engineers/Association for Computing Machinery (IEEE/ACM) Internal Conference for High-Performance Computing, Networking, Storage and Analysis 2013 (SC'13). He received core grant awards from the National Science Foundation (NSF) and Department of Energy (DOE), respectively, and the Lawrence Berkeley National Laboratory Award (LBNL) of Excellence. His current research interests include coprocessor architecture (e.g., MIC/GPU), FPGA-based accelerators, advanced computer architecture, and operating systems on emerging non-volatile memory and solid state drive technologies.