[Seminar] Enriching HW/SW Co-design Flows with FPGA-accelerated RTL Simulation
호스트: 김진수 교수 (x7302)
As historic technology scaling is near the end, specialization with hardware accelerators is the only way to sustain performance boost for emerging applications. This trend requires RTL implementation as a standard procedure for computer architecture research as well as final chip products. However, due to the complexity and the heterogeneity of today's SoCs, full-stack system research with RTL is bottlenecked by its low simulation speed.
In this talk, I will present methodologies that accelerate full-system RTL simulation for three V's using FPGAs: performance validation (MIDAS), functional validation (DESSERT), and power/energy validation (Strober+Simmani), powered by compiler passes and statistical techniques. I will also discuss how these methodologies can be useful to address various issues encountered in the HW/SW co-design flow.
Donggyu Kim is a power modeling engineer at Apple. He received his Ph.D. and M.S. in Computer Science from UC Berkeley, and B.S. in CSE and Math from POSTECH. His research interests lie broadly in HW/SW co-design methodologies including computer architecture, performance/power modeling, and verification. His research was highlighted as one of IEEE Micro's Top Picks and another Top Picks Honorable Mention. He was also a recipient of the Presidential Science Scholarship and Kwanjeong Scholarship.