Quad-Chiplet AI SoC with Full-Chip Scalable Mesh Over 16Gb/s UCIe-Advanced Die-to-Die Interface for Large-Scale AI Inferencing
요약
This chip uses a scalable chiplet-based architecture that defines the minimum system granularity, enabling the construction of a large, virtually monolithic system. Modular chiplets support both scale-up and scale-out expansion, allowing growth from single-die setups to multi-chiplet clusters.The architecture combines a chiplet-based design, low-latency die-to-die interfaces, unified mixed-precision compute, holistic synchronization, and HBM3E with advanced power schemes to sustain bandwidth, capacity, and thermal stability.
연사 소개
Rebellions CTO