​Recent advancements in machine learning are re-invigorating nearly every application domain with an eye towards innovation. Due to their integration with machine learning, these systems often require highly efficient domain-specific accelerators to run inference and domain-specific computations. These accelerators are not all the same, because new algorithms are continually being discovered and new applications regularly move into focus. Unfortunately, our ability to quickly build these systems is limited by the expensive cost and tremendous effort required to build a complex accelerator that works in an end-to-end software-hardware system. How can we build these systems with much less effort and cost, and yet still achieve competitive performance and efficiency? In this talk, I will introduce an agile approach to tackle this problem that spans across a set of vertically integrated techniques in compiler, architecture, and VLSI layers to significantly reduce the design effort to b uild domain-specific accelerators and compilers. These techniques are based on coarse-grained reconfigurable arrays (CGRA), a flexible architectural template that can be specialized towards many different application domains. I will also introduce a set of silicon prototypes taped out in advanced node technologies that demonstrate the approach while targeting the acceleration of dense and sparse applications.​

​Christopher Torng is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Southern California (USC). Prior to his appointment, he was a postdoctoral researcher at Stanford University operating in the leadership of the Stanford AHA Agile Hardware Project, where he worked on creating high-performance and energy-efficient architectures for domain-specific hardware acceleration supported by an agile software-hardware co-design methodology. He received his Ph.D. degree from Cornell University in electrical and computer engineering. He has over ten years of experience taping out complex digital SoCs, while also building new agile flow tools that have already supported chip tapeouts for dozens of silicon prototypes in technologies ranging from 180nm down to 12nm for research and teaching. His activities have resulted in his selection as a Rising Star in Computer Architecture by Georgia Tech as well as an IEEE MICRO Top Pick from Hot Chips.​