The Compute Express Link (CXL) has recently gained attention in the technology community due to its promising capabilities in managing hardware heterogeneity and streamlining resource disaggregation. While there are currently no commercial products or platforms that integrate CXL 2.0/3.0 into memory pooling, it is expected to substantially enhance memory resource disaggregation in the near future. In this talk, we will provide an overview of CXL, explaining its importance and discussing the current state of the industry through the lens of a real-world example.

During the presentation, we will delve into the reasons behind the need for a new interface for cache coherence in existing computing and memory resources. We will also explore how CXL can play a pivotal role in integrating various types of resources into a disaggregated pool. To better illustrate this concept, we will discuss two real-world system examples: the first, a CXL 2.0-based end-to-end system that establishes a direct connection between a host processor complex and remote memory resources using CXL's memory protocol; the second, a prototype storage expansion system that incorporates CXL technology for enhanced performance.

In the final segment of our talk, we will briefly introduce an array of hardware prototypes specifically designed to support future CXL systems (CXL 3.0). These prototypes are part of our ongoing project aimed at advancing the development and adoption of CXL technology in the industry.

Dr. Myoungsoo Jung is a tenured Associate Professor at KAIST and leads the CAMEL research group (http://camelab.org). He is also the CEO and Founder of Panmnesia, a KAIST-based start-up (https://panmnesia.com/). Dr. Jung obtained his Ph.D. in Computer Science from Pennsylvania State University, his M.S. in Computer Science from Georgia Institute of Technology, and an M.S. in Embedded Systems from Korea University. With extensive industry experience, Dr. Jung holds numerous U.S. patents related to multi-channel SSDs and has authored over a hundred research papers on SSD flash firmware and kernel-level file systems. His work has been published in leading conferences, including OSDI, ISCA, MICRO, ASPLOS, FAST, USENIX ATC, and HPCA. Dr. Jung has received core grant awards from the National Science Foundation (NSF), Department of Energy (DOE), and National Research Foundation (NRF). In recognition of his outstanding contributions, he has been honored with the Lawrence Berkeley National Laboratory Award (LBNL) of Excellence, NVMW Memorable Paper Award (2022), and Samsung Best Paper Award (2022). Dr. Jung's current research interests encompass cache coherent interconnects (such as CXL), coprocessor architecture, FPGA-based accelerators, advanced computer architecture, and operating systems on emerging non-volatile memory and solid-state drive technologies.