​This talk will explore the system architecture of NVMe-oF (NVMe over Fabrics), with a particular focus on the performance bottlenecks encountered when processing AI workloads. To satisfy recently emerging demand of workload requirements, we will analyze a range of optimization techniques applied in the NVMe-oF layers (i.e., Transport layer and NVMe-oF protocol layer) with a consideration of a software/hardware codesign in SmartNIC. This talk will review various SmartNIC solutions from different vendors. This comprehensive analysis will inform the design of a future SmartNIC architecture for an AI storage system.​

​Ph.D. in Computer Science and Engineering with 10+ years of SDN experience, focused on optimizing networking stacks across hardware and software in distributed systems for high-performance workloads. Expert in programmable data plane technologies, including Tofino ASIC, SmartNIC, and DPDK. Proven ability to make critical technical design decisions and to deliver practical solutions on time through research, development, and technical leadership. Connected with peers from academia, industry, and open-source communities.
​2025-Present KT Cloud
​2023-2025: Intel / Technical Lead in IPU team
​2020-2023: Barefoot Networks / Software Enginner
​2015-2020: SK Telecom / Research Engineer​